sequential circuit造句
例句與造句
- Verification of sequential circuit design based on obdd
時(shí)序電路設(shè)計(jì)的驗(yàn)證 - Asynchronous transmission sequential circuit
傳送信號(hào)減衰 - Asynchronous sequential circuit
異步時(shí)序電路 - Autonomous sequential circuit
自激時(shí)序電路 - We also develop a new word - level fault parallel fs algorithin for synchronous sequential circuits
接著又開發(fā)了一個(gè)新的單機(jī)字級(jí)故障并行fs算法。 - It's difficult to find sequential circuit in a sentence. 用sequential circuit造句挺難的
- The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究?jī)?nèi)容正是面向非掃描同步時(shí)序電路的并行atpg算法。 - Most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm )
Vlsi系統(tǒng)中大部分是時(shí)序電路，時(shí)序電路可以用符號(hào)化的有限狀態(tài)機(jī)( finite - state - machine ，簡(jiǎn)稱fsm )來(lái)模擬。 - Although some scholars have done lots of work on the test generation of the digital circuits , it is still a well - known puzzle to test sequential circuits
雖然各國(guó)學(xué)者在數(shù)字電路測(cè)試生成上已做了大量的工作，時(shí)序電路的測(cè)試生成仍然是公認(rèn)的難題。 - The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations , which resulted in the complexity of the sequential circuit
在高速時(shí)鐘和低速時(shí)鐘的情況下，系統(tǒng)有不同的時(shí)序要求，這就決定了時(shí)序電路的復(fù)雜性。 - The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm , and the results are better than other algorithms "
采用國(guó)際標(biāo)準(zhǔn)時(shí)序電路iscas ’ 89 (包括addendum ’ 93 )進(jìn)行了算法驗(yàn)證，取得了優(yōu)于文獻(xiàn)中其它算法的結(jié)果。 - Optimize synchronous sequential circuit with retiming was introduced by leiserson and saxe in 1983 , and retiming optimizational algorithm was summarized comprehensively in 1991
Leiserson和saxe于1983年提出了利用重定時(shí)優(yōu)化同步時(shí)序電路，并于1991年對(duì)重定時(shí)優(yōu)化算法做了全面的總結(jié)。 - The automatic test vector generation method based on fault simulation is described , and the whole procedure of atpg of sequential circuits is analyzed , fault simulator - hope as an example
本文闡述了基于模擬的自動(dòng)測(cè)試生成方法，以故障模擬器? hope為例分析了整個(gè)時(shí)序電路自動(dòng)測(cè)試生成過(guò)程。 - In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper
本文對(duì)重定時(shí)算法進(jìn)行了深入研究，目的在于消除同步時(shí)序電路的時(shí)序沖突，從而縮短集成電路的設(shè)計(jì)時(shí)間。 - To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
為抑制時(shí)序電路中的冗余現(xiàn)象，研究了時(shí)序電路的門控時(shí)鐘技術(shù)，并利用t型觸發(fā)器進(jìn)行時(shí)序電路設(shè)計(jì)。 - Base on the existing synchronous sequential circuits fault simulator - hope , the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly
本文在同步時(shí)序電路故障模擬器? hope的基礎(chǔ)上，率先對(duì)基于螞蟻算法的時(shí)序電路測(cè)試矢量生成方法作了系統(tǒng)的開拓性研究。
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